Sensible Hardware Configurations

The default configuration of gem5 is not always sensible or realistic, which makes it necessary to modify it to arrive at meaningful conclusions.

Group	Parameter	File path	Corresponding variable	Default value	Sensible value(s)
CPU
CPU
Cache	L1 assoc	configs/common/Caches.py	L1Cache.assoc	2	8
Cache	L1 tag latency	configs/common/Caches.py	L1Cache.tag_latency	2	1
Cache	L1 data latency	configs/common/Caches.py	L1Cache.data_latency	2	1
Cache	L1 response latency	configs/common/Caches.py	L1Cache.response_latency	2	1
Cache	L1 MSHRs	configs/common/Caches.py	L1Cache.mshrs	4	128
Cache	L1 targets per MSHR	configs/common/Caches.py	L1Cache.tgts_per_mshr	16
Cache	L1 write buffers	configs/common/Caches.py	L1Cache.write_buffers	undefined	56
Cache	L2 assoc	configs/common/Caches.py	L2Cache.assoc	8	4
Cache	L2 tag latency	configs/common/Caches.py	L2Cache.tag_latency	20	14
Cache	L2 data latency	configs/common/Caches.py	L2Cache.data_latency	20	14
Cache	L2 response latency	configs/common/Caches.py	L2Cache.response_latency	20	1
Cache	L2 MSHRs	configs/common/Caches.py	L2Cache.mshrs	20	256
Cache	L2 targets per MSHR	configs/common/Caches.py	L2Cache.tgts_per_mshr	12	16
Cache	L2 write buffers	configs/common/Caches.py	L2Cache.write_buffers	8	256
Cache	L3 assoc	configs/common/Caches.py	L3Cache.assoc	undefined	16
Cache	L3 tag latency	configs/common/Caches.py	L3Cache.tag_latency	undefined	44
Cache	L3 data latency	configs/common/Caches.py	L3Cache.data_latency	undefined	44
Cache	L3 response latency	configs/common/Caches.py	L3Cache.response_latency	undefined	1
Cache	L3 MSHRs	configs/common/Caches.py	L3Cache.mshrs	undefined	256
Cache	L3 targets per MSHR	configs/common/Caches.py	L3Cache.tgts_per_mshr	undefined	16
Cache	L3 write buffers	configs/common/Caches.py	L3Cache.write_buffers	undefined	256
Cache
TLB
TLB

Configuration of Intel Skylake microarchitecture can be found here.